1. Field of the Invention
The invention relates to microelectronic semiconductor devices, and more particularly to methods for fabricating semiconductor devices with selective stress memory effect thereon.
2. Description of the Related Art
Semiconductor fabrication techniques, such as stress memory technique (SMT) and selective stress memory technique (SSMT) can be adopted after S/D implantation to induce stress in MOSFET channel, thereby improving device performance for advanced technologies (e.g. 65 nm generations or beyond). The SMT or SSMT consists of gate polysilicon recrystallization under a stress capping layer using S/D annealing, leading to an improved NMOS performance of 6-10%. Depending on the materials utilized, it may be necessary to remove the capping layer on the PMOS before S/D annealing.
Conventional SMT process uses stressed film deposition and S/D annealing to apply the stress to the substrate. The stressed film is then removed prior to subsequent processes. Alternatively, different stresses, generated by different capped layers with different thicknesses, referred to as selective stress memory technique (SSMT), may be respectively applied to an NMOS field effect transistor and a PMOS field effect transistor. Some devices require a resist protection oxide (RPO) layer to define silicide and non-silicide regions. The RPO process is performed subsequent to the SSMT process but prior to the silicide process.
FIGS. 1A-1H are cross sections illustrating fabrication of a conventional semiconductor device with selective stress memory effect. In FIG. 1A, a semiconductor substrate 10 including a bulk silicon substrate or a silicon-on-insulator (SOI) substructure is provided. The substrate 10 preferably includes a monocrystalline silicon substrate doped to a p-well for an NMOS device 100N or to an n-well for a PMOS device 100P. The substrate 10 has a first well of the first conductivity and a second well of the second conductivity. The first well and the second well are isolated from one another by shallow trench isolation (STI) 45 in the substrate 10 to separate PMOS transistor 100P from NMOS transistor 100N. Gate dielectric 15 is deposited on the surface of the semiconductor substrate 10 over both the PMOS transistor 100P and the NMOS transistor 100N. Gate electrode 20 such as doped silicon is deposited and formed on gate dielectric 15 over both the PMOS transistor 100P and the NMOS transistor 100N. Insulating sidewall spacers such as oxide-nitride-oxide (ONO) structures 32, 34, and 36 are formed on the sidewalls of the gate electrode 20 over both the PMOS transistor 100P and the NMOS transistor 100N. Ion implantation 50 is performed to create source 44 and drain 42 in the substrate 10. The source 44 and drain 42 over the PMOS transistor 100P are inverted doping types corresponding to those over the NMOS transistor 100N.
Referring to FIG. 1B, a first dielectric layer 60 and a second dielectric layer 65 are sequentially formed on the substrate over both the PMOS transistor 100P and the NMOS transistor 100N.
Referring to FIG. 1C, a mask (not shown) is disposed over the NMOS transistor 100N, thereby exposing the second dielectric layer 65 over the PMOS transistor 100P. An etching process is performed to thin the exposed second dielectric layer 65. Different stresses are thus selectively generated over either the PMOS transistor 100P or the NMOS transistor 100N.
Referring to FIG. 1D, the second dielectric layer 65 is removed by wet etching or dry etching. The first dielectric layer 60 is sequentially removed by wet etching. The ONO or ON sidewalls are undercut as the first dielectric layer 60 is etched, creating a recess 38a, as shown in FIG. 1E.
To meet device requirements, a resist protection oxide (RPO) layer is sometimes provided to define silicide and non-silicide regions. The RPO process is performed after the SMT or SSMT process but before the metal silicide process. For example, some semiconductor devices comprise a main region for a memory matrix and a peripheral region for logic control. The peripheral logic region must be silicidized to reduce contact resistance, while silicidization of the main region is not necessary.
FIGS. 1F-1H show cross sections illustrating a silicidization process over the main region. Referring to FIG. 1F, a passivation layer 70 is conformably formed on the substrate 10 over both the PMOS transistor 100P and the NMOS transistor 100N. The passivation layer 70 over the peripheral logic region desirable for carrying out silicidization is removed, while the passivation layer 70 covering the main region remains.
A mask (not shown) is disposed over the main region and the exposed passivation layer over the peripheral logic region is removed. The exposed passivation layer is etched by wet etching, resulting in further undercut of the ONO or ON sidewalls creating a second recess 38b, as shown in FIG. 1G.
Referring to FIG. 1H, a metal silicide layer 80 is formed over both the PMOS transistor 100P and the NMOS transistor 100N of the peripheral logic region. The metal silicide layer 80 is formed directly contacting the gate electrode 20 and source 42 and drain region 44.
Although a conventional SMT process can improve device performance by applying a stress thereon, the additional process will result in higher fabrication cost and reducing the process window or margin. The higher fabrication cost results from the cost of the additional process steps (e.g., SMT/SSMT film deposition or removal, RPO deposition and removal). The process window or margin will be reduced due to the multi-step film deposition and etching process possibly resulting in higher leakage current induced by a severe STI divot and spacer undercut.